Static random access memories (“SRAM”) include a plurality of cells disposed in rows and columns to form an array. Conventional SRAM cells include a plurality of transistors coupled to bit lines and word lines that are used to read and write a bit of data to the memory cell. However, conventional SRAM cells suffer from half-select disturbance in which all the cells on the same row, which is controlled by a common word line, are simultaneously activated when only a cell in a single column is to be accessed (i.e., data being read from or written to the cell). The half-select disturbance may result in data corruption of the cells not being accessed due to their half-selection (i.e., the word line to which they are coupled being set to a logic “1” or “high”). Additionally, conventional SRAM cells typically exhibit poor current performance during VCCmin operation (the operation of the SRAM under the lowest possible voltage under which the SRAM may reliably be operated).